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Philips Semiconductors FAST Products
Product specification
Arithmetic logic unit
74F181
FEATURES
* Provides 16 arithmetic operation: add, subtract, compare, and
double; plus 12 other arithmetic operations
PIN CONFIGURATION
B0 1 A0 S3 S2 S1 S0 Cn M 2 3 4 5 6 7 8 9 24 VCC 23 A1 22 B1 21 A2 20 B2 19 A3 18 B3 17 G 16 C n+4 15 P 14 A=B 13 F3
* Provides all 16 logic operations of two variables: Exclusive-OR,
Compare, AND, NAND, NOR, OR, plus 10 other logic operations
* Full look-ahead carry for high speed arithmetic operation on long
words
* 40% faster than 'S181 with only 30% 'S181 power consumption * Available in 300mil-wide Slim 24-pin Dual In-Line package
DESCRIPTION
The 74F181 is a 4-bit high-speed parallel Arithmetic Logic Unit (ALU). Controlled by the four Function Select inputs (S0-S3) and the Mode Control input (M), it can perform all the 16 possible logic operations or 16 different arithmetic operations on active-High or active-Low operands. The Function Table lists these operations.
F0
F1 10 F2 11 GND 12
SF00193
TYPE 74F181
TYPICAL PROPAGATION DELAY 7.0ns
TYPICAL SUPPLY CURRENT (TOTAL) 43mA
ORDERING INFORMATION
DESCRIPTION 24-Pin Plastic Slim DIP (300 mil) 24-Pin Plastic SOL COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F181N N74F181D
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS A0-A3 B0-B3 M S0-S3 Cn Cn+4 P G A=B F0-F3 NOTE: DESCRIPTION A operand inputs B operand inputs Mode control input Function select input Carry input Carry output Carry Propagate output Carry Generate output Compare output Outputs 74F (U.L.) HIGH/LOW 1.0/3.0 1.0/3.0 1.0/1.0 1.0/4.0 1.0/5.0 50/33 50/33 50/33 OC/33 50/33 LOAD VALUE HIGH/LOW 20A/1.8mA 20A/1.8mA 20A/0.6mA 20A/2.4mA 20A/3.0mA 1.0mA/20mA 1.0mA/20mA 1.0mA/20mA OC/20mA 1.0mA/20mA
One (1.0) FAST unit load is defined as: 20A in the High state and 0.6mA in the Low state. OC = Open Collector
March 3, 1989
1
853-0351 95947
Philips Semiconductors FAST Products
Product specification
Arithmetic logic unit
74F181
LOGIC SYMBOL
Active-High Operands
2 1 23 22 21 20 19 18
IEC/IEEE SYMBOL
6 5 4 3
0 M 4 CI P0 Q0 P1 Q1 P2 Q2 P3 Q3
ALU [T] 0 21 P=G CP CG CO 15 17 16 14
A0 B0 A1 B1 A2 B2 A3 B3 7 8 6 5 4 3 Cn M S0 S1 S2 S3 F0 F1 F2 F3 Cn+4 A=B G P 16 14 17 15
8 7 2 1 23 22 21 20 19 18
9 10 11 13
9
10 11 13
SF00197
Active-Low Operands
2 1 23 22 21 20 19 18
A0 B0 A1 B1 A2 B2 A3 B3 7 8 6 5 4 3 Cn M S0 S1 S2 S3 F0 F1 F2 F3 Cn+4 A=B G P 16 14 17 15
VCC = Pin 24 GND = Pin 12
9
10 11 13
SF00196
March 3, 1989
2
Philips Semiconductors FAST Products
Product specification
Arithmetic logic unit
74F181
LOGIC DIAGRAM
S0 S1 S2 S3 B3 6 5 4 3 18 17 G
16 A3 19
Cn+4
B2
20
15
P
A2
21 13 F3
B1
22
A1
23
11
F2
B0
1 14 A=B
10 A0 M Cn 2 8 9 7
F1
F0
VCC = Pin 24 GND = Pin 12
SF00194
March 3, 1989
3
Philips Semiconductors FAST Products
Product specification
Arithmetic logic unit
74F181
When the Mode Control input (M) is High, all internal carries are inhibited and the device performs logic operations on the individual bits as listed. When the Mode control input is Low, the carries are enabled and the device performs arithmetic operations on the two 4-bit words. The device incorporates full internal carry look-ahead and provides for either ripple carry between device using the Cn+4 output, or for carry look-ahead between packages using the signals P (Carry Propagate) and G (Carry Generate). P and G are not affected by carry in. When speed requirements are not stringent, it can be used in a simple ripple carry mode by connecting the Carry output (Cn+4) signal to the Carry input (Cn) of the next unit. For high-speed operation, the device is used in conjunction with the 74F182 carry look-ahead circuit. One carry look-ahead package is required for each group of four 74F181 devices. Carry look-ahead can be provided at various levels and offers high speed capability over extremely long word lengths. The A=B output from the device goes High when all four F outputs are High and can be used to indicate logic equivalence over 4-bits
when the unit is in the subtract mode. The A=B output is open-collector and can be wired-AND with other A=B outputs to give a comparison for more than 4 bits. The A=B signal can also be used with the Cn+4 signal to indicate A>B and AMODE-SELECT FUNCTION TABLE
MODE SELECT INPUTS S3 L L L L L L L L H H H H H H H H H L * ** = = = = S2 L L L L H H H H L L L L H H H H S1 L L H H L L H H L L H H L L H H S0 L H L H L H L H L H L H L H L H ACTIVE HIGH INPUTS & OUTPUTS Logic (M=H) A A+B AB Logical 0 AB B AB AB A+B AB B AB Logical 1 A+B A+B A Arithmetic** (M=L) (Cn=H) A A+B A+B minus 1 A plus AB (A+B) plus AB A minus B minus 1 AB minus 1 A plus AB A plus B (A+B) plus AB AB minus 1 A plus A* (A+B) plus A (A+B) plus A A minus 1 ACTIVE LOW INPUTS & OUTPUTS Logic (M=H) A AB A+B Logical 1 A+B B AB A+B AB AB B A+B Logical 0 AB AB A Arithmetic** (M=L) (Cn=L) A minus 1 AB minus 1 AB minus 1 minus 1 A plus (A+B) AB plus (A+B) A minus B minus 1 A+B A plus (A+B) A plus B AB plus (A+B) A+B A plus A* AB plus A AB plus A A
High voltage level Low voltage level Each bit is shifted to the next more significant position. Arithmetic operations expressed in two's complement notation.
March 3, 1989
4
Philips Semiconductors FAST Products
Product specification
Arithmetic logic unit
74F181
Table 1. Sum Mode Test
Function Inputs: S0 = S3 = 4.5V, S1 = S2 = M = 0V PARAMETER tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL INPUT UNDER TEST Ai Bi Ai Bi Ai Bi Ai Bi Cn OTHER INPUT, SAME BIT Apply 4.5V Bi Ai Bi Ai None None None None None Apply GND None None None None Bi Ai Bi Ai None OTHER DATA INPUTS Apply 4.5V Remaining A and B Remaining A and B None None Remaining B Remaining B Remaining B Remaining B All A Apply GND Cn Cn Remaining A, B, Cn Remaining A, B, Cn Remaining A, Cn Remaining A, Cn Remaining A, Cn Remaining A, Cn All B OUTPUT UNDER TEST Fi Fi P P G G Cn+4 Cn+4 Any F or Cn+4
Table 2. Diff Mode Test
Function Inputs: S1 = S2 = 4.5V, S0 = S3 = M = 0V PARAMETER tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL INPUT UNDER TEST Ai Bi Ai Bi Ai Bi Ai Bi Ai Bi Cn OTHER INPUT, SAME BIT Apply 4.5V None Ai None Ai Bi None None Ai Bi None None Apply GND Bi None Bi None None Ai Bi None None Ai None OTHER DATA INPUTS Apply 4.5V Remaining A Remaining A None None None None Remaining A Remaining A None None All A and B Apply GND Remaining B, Cn Remaining B, Cn Remaining A, B, Cn Remaining A, B, Cn Remaining A, B, Cn Remaining A, B, Cn Remaining B, Cn Remaining B, Cn Remaining A, B, Cn Remaining A, B, Cn None OUTPUT UNDER TEST Fi Fi P P G G A=B A=B Cn+4 Cn+4 Any F or Cn+4
Table 3. Logic Mode Test
Function Inputs: S1 = S2 = 4.5V, S0 = S3 = 0V PARAMETER tPLH, tPHL tPLH, tPHL INPUT UNDER TEST Ai Bi OTHER INPUT, SAME BIT Apply 4.5V Bi Ai Apply GND None None OTHER DATA INPUTS Apply 4.5V None None Apply GND Remaining A, B, Cn Remaining A, B, Cn OUTPUT UNDER TEST Fi Fi
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature range PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to VCC 40 0 to +70 -65 to +150 UNIT V V mA V mA C C
March 3, 1989
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Philips Semiconductors FAST Products
Product specification
Arithmetic logic unit
74F181
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VIH VIL IIK VOH IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High level output voltage High-level output current Low-level output current Operating free-air temperature range 0 A=B only Any output except A=B PARAMETER MIN 4.5 2.0 0.8 -18 4.5 -1 20 +70 NOM 5.0 MAX 5.5 V V V mA V mA mA C UNIT
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL IOH VOH PARAMETER High-level output current High-level output voltage A=B only Any output except A=B TEST CONDITIONS1 VCC = MIN, VIL = MAX; VIH = MIN, VOH = MAX VCC = MIN, VIL = MAX, VIH = MIN VCC = MIN, VIL = MAX, VIH = MIN VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V M A0-A3, B0-B3 IIL Low-level input current S0-S3 Cn IOS Short-circuit output current3 Any output except A=B ICCH ICC Supply current (total) ICCL VCC = MAX VCC = MAX S0-S3=M=A0-A3=4.5V, B0-B3=Cn=GND S0-S3=M=4.5V, B0-B3=Cn=A0-A3=GND -60 43 43 VCC = MAX, VI = 0.5V IOH = MAX 10%VCC 5%VCC 10%VCC 5%VCC 2.5 V 2.7 3.4 0.30 0.30 -0.73 0.50 V 0.50 -1.2 100 20 -0.6 -1.8 -2.4 -3.0 -150 65 65 V A A mA mA mA mA mA mA mA LIMITS MIN TYP2 MAX 250 UNIT A
VOL VIK II IIH
Low-level output voltage Input clamp voltage Input current at maximum input voltage High-level input current
IOL = MAX
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
March 3, 1989
6
Philips Semiconductors FAST Products
Product specification
Arithmetic logic unit
74F181
AC ELECTRICAL CHARACTERISTICS
LIMITS TEST CONDITIONS SYMBOL PARAMETER VCC = +5.0V Tamb = +25C CL = 50pF RL = 500 Condition M=0V M=S1=S2=0V, S0=S3=4.5V M=S0=S3=0V, S1=S2=4.5V M=0V M=S1=S2=0V, S0=S3=4.5V M=S0=S3=0V, S1=S2=4.5V M=S1=S2=0V, S0=S3=4.5V M=S0=S3=0V, S1=S2=4.5V M=S1=S2=0V, S0=S3=4.5V M=S0=S3=0V, S1=S2=4.5V MIN 3.0 2.5 5.0 5.0 5.0 5.0 3.0 3.0 3.0 3.0 3.0 3.0 2.5 3.0 2.5 3.0 3.0 3.0 3.0 3.0 3.5 3.5 4.0 4.5 M=4.5V M=S0=S3=0V, S1=S2=4.5V 3.5 3.5 10.0 6.0 TYP 5.0 5.0 9.0 8.0 9.5 8.0 5.0 5.0 5.0 5.0 4.5 5.0 4.0 4.5 4.0 5.0 4.5 4.5 4.5 5.0 6.0 5.5 6.5 7.0 5.5 5.5 14.0 8.5 MAX 8.0 8.0 12.0 12.0 13.0 12.0 8.0 8.0 7.5 7.5 8.0 8.5 7.0 7.5 7.5 8.5 7.5 7.5 8.5 8.5 10.0 9.5 10.5 10.5 9.0 10.0 19.0 12.5 VCC = +5.0V 10% Tamb = 0C to +70C CL = 50pF RL = 500 MIN 3.0 2.5 5.0 5.0 5.0 5.0 3.0 2.5 2.5 2.5 2.5 2.5 2.0 2.5 2.0 2.5 2.5 3.0 2.5 3.0 3.0 3.0 3.5 4.5 3.0 3.0 9.5 5.5 MAX 8.5 8.5 13.0 12.5 14.0 12.5 9.0 9.0 8.0 8.0 9.0 9.5 7.5 8.0 8.0 9.0 8.5 8.5 9.0 9.0 11.0 10.0 11.0 11.0 9.5 10.5 20.5 12.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
UNIT
Mode tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Propagation delay Cn to Cn+4 Propagation delay An or Bn to Cn+4 Propagation delay An or Bn to Cn+4 Propagation delay Cn to Fn Propagation delay An or Bn to G Propagation delay An or Bn to G Propagation delay An or Bn to P Propagation delay An or Bn to P Propagation delay Ai or Bi to Fi Propagation delay Ai or Bi to Fi Propagation delay An or Bn to Fn Propagation delay An or Bn to Fn Propagation delay Ai or Bi to Fi Propagation delay An or Bn to A=B Sum Diff Sum Diff Diff Sum Sum Diff Sum Diff Sum Diff Sum Diff Logic Diff
Table 1 2 1 2 2 1 1 2 1 2 1 2
Waveform 1 2 2 1 1 2 2 1, 2 1, 2 1, 2 1, 2 1, 2
3 2
1, 2 1, 2
NOTES: "An or Bn to Fn" means any A or any B to any F; "Ai or Bi to Fi" means A1, B1 to F1; A2, B2 to F2 (the identifying number must be the same).
March 3, 1989
7
Philips Semiconductors FAST Products
Product specification
Arithmetic logic unit
74F181
AC ELECTRICAL CHARACTERISTICS
LIMITS TEST CONDITIONS SYMBOL PARAMETER VCC = +5.0V Tamb = +25C CL = 50pF RL = 500 MIN 3.5 3.5 3.0 3.0 10.5 6.0 10.0 5.5 3.5 3.0 2.5 2.5 2.5 2.5 3.5 3.5 4.5 4.0 3.5 3.5 4.0 4.0 12.0 6.5 13.0 6.5 11.5 6.0 13.0 6.0 TYP 5.5 5.0 5.5 5.5 16.5 8.0 15.0 8.5 7.0 5.5 5.0 4.0 4.0 4.5 6.0 6.0 7.0 6.0 6.0 6.0 7.0 6.0 16.0 8.0 17.0 8.0 16.0 8.0 17.0 8.0 MAX 8.0 8.0 8.5 8.5 22.5 11.0 19.0 12.5 11.0 10.0 7.5 7.5 6.5 7.0 8.5 8.5 10.0 9.5 8.5 8.5 10.0 9.5 20.0 11.0 21.0 10.5 20.0 10.5 21.5 11.0 VCC = +5.0V 10% Tamb = 0C to +70C CL = 50pF RL = 500 MIN 3.0 3.0 3.0 3.0 10.5 6.0 10.0 5.0 3.0 2.5 2.5 2.5 2.5 2.5 3.5 3.5 4.5 4.0 3.5 3.5 4.0 4.0 11.0 6.0 12.0 6.0 10.5 6.0 12.5 6.0 MAX 9.0 9.0 9.5 9.5 24.0 11.5 21.0 13.5 12.5 10.0 8.0 8.0 7.0 8.0 9.5 9.5 11.0 10.0 9.5 9.5 11.5 10.0 22.0 11.0 24.0 11.5 22.0 11.0 24.0 11.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
UNIT
Mode tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Propagation delay Si to Fi (Inverting) Propagation delay Si to Fi (Non-Inverting) Propagation delay Si to A=B (Inverting) Propagation delay Si to A=B (Non-Inverting) Propagation delay Si to Cn+4 (Inverting) Propagation delay Si to G (Non-Inverting) Propagation delay Si to P (Non-Inverting) Propagation delay M to Fi (Inverting) Propagation delay M to Fi (Non-Inverting) Propagation delay M to Fi (Inverting) Propagation delay M to Fi (Non-Inverting) Propagation delay M to A=B (Inverting) Propagation delay M to A=B (Non-Inverting) Propagation delay M to A=B (Inverting) Propagation delay M to A=B (Non-Inverting) Sum Sum Diff Diff Sum Sum Diff Diff
Waveform 1 2 1 2 1 2 2 1 2 1 2 1 2 1 2
AC WAVEFORMS
For all waveforms, VM = 1.5V.
VIN
VM tPLH
VM tPHL
VIN
VM tPHL
VM tPLH
VOUT
VM
VM
VOUT
VM
VM
SF00092
SF00093
Waveform 1. Propagation Delay for Non-Inverting Paths
Waveform 2. Propagation Delay for Inverting Paths
March 3, 1989
8
Philips Semiconductors FAST Products
Product specification
Arithmetic logic unit
74F181
TEST CIRCUIT AND WAVEFORMS
VCC 7.0V VIN PULSE GENERATOR RT D.U.T. VOUT RL NEGATIVE PULSE 90% VM 10% tTHL (tf ) CL RL tTLH (tr ) 90% POSITIVE PULSE 10% tTHL (tf ) AMP (V) 90% VM tw 10% 0V tw VM 10% tTLH (tr ) 0V AMP (V)
90%
Test Circuit for Open Collector Outputs SWITCH POSITION TEST Open Collector All other SWITCH closed open
VM
Input Pulse Definition
DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00195
March 3, 1989
9

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